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» Floorplanning for Partial Reconfiguration in FPGAs
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ISLPED
2007
ACM
79views Hardware» more  ISLPED 2007»
15 years 21 days ago
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs
Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen...
ARCS
2005
Springer
15 years 4 months ago
An FPGA Dynamically Reconfigurable Framework for Modular Robotics
Dynamic Reconfiguration has always constituted a challenge for embedded systems designers. Nowadays, technological developments make possible to do it on Xilinx FPGAs, but setting...
Andres Upegui, Rico Moeckel, Elmar Dittrich, Auke ...
ICCD
2006
IEEE
157views Hardware» more  ICCD 2006»
15 years 8 months ago
Dynamic Co-Processor Architecture for Software Acceleration on CSoCs
By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software an...
Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A...
DATE
2010
IEEE
174views Hardware» more  DATE 2010»
15 years 4 months ago
VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems
- Due to the runtime flexibility offered by field programmable gate arrays (FPGAs), FPGAs are popular devices for stream processing systems, since many stream processing applicatio...
Abelardo Jara-Berrocal, Ann Gordon-Ross
IPPS
2007
IEEE
15 years 5 months ago
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one st...
Christopher Claus, Florian Helmut Müller, Joh...