45 search results - page 4 / 9 » Floorplanning with Pin Assignment |
ISPD
2009
ACM
15 years 4 months ago
2009
ACM
ITC
2003
IEEE
15 years 2 months ago
2003
IEEE
Backside light emission and electrical measurements were used to evaluate the susceptibility to latchup of externally cabled I/O pins for a 0.13 µm technology generation [1,2] te...
ASPDAC
2004
ACM
15 years 1 months ago
2004
ACM
Abstract - We propose an integrated archltectural/physicdplanning approach named priority assignment optimization to mioimize the current surge in high performance power eifkient c...
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
Gate oxide tunneling current (Igate) is emerging as a key roadblock for device scaling in nanometer-scale CMOS circuits. A practical means to reduce Igate is to leverage dual Tox ...
ASPDAC
1999
ACM
15 years 1 months ago
1999
ACM
A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on...