578 search results - page 37 / 116 » Flow Map Layout |
ICCAD
1994
IEEE
15 years 4 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
101
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IPPS
2007
IEEE
15 years 6 months ago
2007
IEEE
Implementing real-time video processing systems put high requirements on computation and memory performance. FPGAs have proven to be effective implementation architecture for thes...
102
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HICSS
2006
IEEE
15 years 5 months ago
2006
IEEE
This paper addresses challenges associated with the dynamics of knowledge in clusters and regional networks. It develops a conceptual framework, a methodology and a research agend...
109
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MICRO
2000
IEEE
15 years 3 months ago
2000
IEEE
Functionality and performance of EPIC architectural features depend on extensive compiler support. Predication, one of these features, promises to reduce control flow overhead and...
101
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MJ
2006
14 years 11 months ago
2006
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity ...