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» Functional test generation for non-scan sequential circuits
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CEC
2005
IEEE
15 years 3 months ago
Dynamic power minimization during combinational circuit testing as a traveling salesman problem
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
Artem Sokolov, Alodeep Sanyal, L. Darrell Whitley,...
EDCC
2005
Springer
15 years 3 months ago
PathCrawler: Automatic Generation of Path Tests by Combining Static and Dynamic Analysis
Abstract. We present the PathCrawler prototype tool for the automatic generation of test-cases satisfying the rigorous all-paths criterion, with a user-defined limit on the number...
Nicky Williams, Bruno Marre, Patricia Mouy, Muriel...
ITC
1998
IEEE
120views Hardware» more  ITC 1998»
15 years 2 months ago
Test generation in VLSI circuits for crosstalk noise
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital c...
Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer
DAC
2009
ACM
15 years 10 months ago
On systematic illegal state identification for pseudo-functional testing
The discrepancy between integrated circuits' activities in normal functional mode and that in structural test mode has an increasing adverse impact on the effectiveness of ma...
Feng Yuan, Qiang Xu
DFT
2003
IEEE
98views VLSI» more  DFT 2003»
15 years 3 months ago
Constrained ATPG for Broadside Transition Testing
In this paper, we propose a new concept of testing only functionally testable transition faults in Broadside Transition testing via a novel constrained ATPG. For each functionally...
Xiao Liu, Michael S. Hsiao