This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
New applications and standards are first conceived only for functional correctness and without concerns for the target architecture. The next challenge is to map them onto an arch...
Dynamic Reconfiguration has always constituted a challenge for embedded systems designers. Nowadays, technological developments make possible to do it on Xilinx FPGAs, but setting...
Andres Upegui, Rico Moeckel, Elmar Dittrich, Auke ...
Reconfigurable hardware is ideal for use in Systems-on-a-Chip, as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is ra...
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...