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» Hardware Accelerated Power Estimation
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120
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FPGA
2009
ACM
154views FPGA» more  FPGA 2009»
15 years 10 months ago
Synthesis of reconfigurable high-performance multicore systems
Reconfigurable high-performance computing systems (RHPC) have been attracting more and more attention over the past few years. RHPC systems are a promising solution for accelerati...
Jason Cong, Karthik Gururaj, Guoling Han
ISCAS
2008
IEEE
115views Hardware» more  ISCAS 2008»
15 years 10 months ago
FSMD partitioning for low power using simulated annealing
— It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partiti...
Nainesh Agarwal, Nikitas J. Dimopoulos
106
Voted
ISLPED
1999
ACM
143views Hardware» more  ISLPED 1999»
15 years 8 months ago
Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
Kanad Ghose, Milind B. Kamble
104
Voted
ICCAD
2007
IEEE
86views Hardware» more  ICCAD 2007»
16 years 15 days ago
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon
—During the power mode transition, a large surge current may lead to the malfunctions in a power-gating design. In this paper, we introduce several important properties of the s...
Yu-Ting Chen, Da-Cheng Juan, Ming-Chao Lee, Shih-C...
ASPDAC
2010
ACM
137views Hardware» more  ASPDAC 2010»
15 years 1 months ago
Improved on-chip router analytical power and area modeling
Over the course of this decade, uniprocessor chips have given way to multi-core chips which have become the primary building blocks of today's computer systems. The presence o...
Andrew B. Kahng, Bill Lin, Kambiz Samadi