104 search results - page 12 / 21 » Hardware Architecture for Fast Camera Effects Rendering |
ISCA
2012
IEEE
13 years 2 days ago
2012
IEEE
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
141
click to vote
DASIP
2010
14 years 4 months ago
2010
In order to obtain depth perception in computer vision, one needs to process pairs of stereo images. This process is computationally challenging to be carried out in real-time as i...
MICRO
2003
IEEE
15 years 2 months ago
2003
IEEE
Abstract—High-speed routers often use commodity, fully-associative, TCAMs (Ternary Content Addressable Memories) to perform packet classification and routing (IP lookup). We prop...
106
Voted
FPGA
2009
ACM
15 years 2 months ago
2009
ACM
This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed archit...
97
Voted
TOG
2008
14 years 9 months ago
2008
Capturing detailed surface geometry currently requires specialized equipment such as laser range scanners, which despite their high accuracy, leave gaps in the surfaces that must ...