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MICRO
2003
IEEE
132views Hardware» more  MICRO 2003»
15 years 11 months ago
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors
Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically req...
Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasa...
HPDC
2007
IEEE
16 years 14 days ago
A statistical approach to risk mitigation in computational markets
We study stochastic models to mitigate the risk of poor Quality-of-Service (QoS) in computational markets. Consumers who purchase services expect both price and performance guaran...
Thomas Sandholm, Kevin Lai
IPPS
2007
IEEE
16 years 13 days ago
File Creation Strategies in a Distributed Metadata File System
As computing breaches petascale limits both in processor performance and storage capacity, the only way that current and future gains in performance can be achieved is by increasi...
Ananth Devulapalli, Pete Wyckoff
164
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CGO
2007
IEEE
15 years 10 months ago
Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors
Dynamic predication has been proposed to reduce the branch misprediction penalty due to hard-to-predict branch instructions. A recently proposed dynamic predication architecture, ...
Hyesoon Kim, José A. Joao, Onur Mutlu, Yale...
WINET
2010
144views more  WINET 2010»
15 years 4 months ago
Cross-layer quality-driven adaptation for scheduling heterogeneous multimedia over 3G satellite networks
Wireless networks are experiencing a paradigm shift from focusing on the traditional data transfer to accommodating the rapidly increasing multimedia traffic. Hence, their schedul...
Hongfei Du, Xiaozheng Huang, Jie Liang, Jiangchuan...
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