38 search results - page 4 / 8 » High-level test synthesis for delay fault testability |
VLSID
1995
IEEE
15 years 3 months ago
1995
IEEE
In this paper, we present methods for synthesizing multi-level asynchronous circuits to be both hazard-free
ATS
2005
IEEE
15 years 5 months ago
2005
IEEE
In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing...
117
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ITC
1994
IEEE
15 years 3 months ago
1994
IEEE
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
ITC
1998
IEEE
15 years 3 months ago
1998
IEEE
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
ETS
2006
IEEE
15 years 5 months ago
2006
IEEE
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...