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» IPR: An Integrated Placement and Routing Algorithm
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DAC
2003
ACM
15 years 4 months ago
Force directed mongrel with physical net constraints
This paper describes a new force directed global placement algorithm that exploits and extends techniques from two leading placers, Force-directed [12] [26] and Mongrel [22]. It c...
Sung-Woo Hur, Tung Cao, Karthik Rajagopal, Yegna P...
ISPD
2005
ACM
151views Hardware» more  ISPD 2005»
15 years 5 months ago
Thermal via placement in 3D ICs
As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promi...
Brent Goplen, Sachin S. Sapatnekar
FPGA
2003
ACM
123views FPGA» more  FPGA 2003»
15 years 4 months ago
Wire type assignment for FPGA routing
The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently dev...
Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun
GLVLSI
2005
IEEE
120views VLSI» more  GLVLSI 2005»
15 years 5 months ago
3D module placement for congestion and power noise reduction
3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today’s mixed signal system integration. In this wo...
Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh
DAC
2007
ACM
16 years 18 days ago
Placement of 3D ICs with Thermal and Interlayer Via Considerations
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...
Brent Goplen, Sachin S. Sapatnekar