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» Improved Simulation of Stabilizer Circuits
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ICCAD
2003
IEEE
205views Hardware» more  ICCAD 2003»
15 years 3 months ago
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
Aseem Agarwal, David Blaauw, Vladimir Zolotov
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
13 years 11 days ago
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures
A significant portion of the energy dissipated in modern integrated circuits is consumed by the overhead associated with timing guardbands that ensure reliable execution. Timing ...
Evgeni Krimer, Patrick Chiang, Mattan Erez
TVLSI
2010
14 years 4 months ago
Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding
By storing more than one bit in each memory cell, multi-level per cell (MLC) NAND flash memories are dominating global flash memory market due to their appealing storage density ad...
Shu Li, Tong Zhang
ISPD
2005
ACM
130views Hardware» more  ISPD 2005»
15 years 3 months ago
Improved algorithms for link-based non-tree clock networks for skew variability reduction
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
Anand Rajaram, David Z. Pan, Jiang Hu
VLSID
1996
IEEE
153views VLSI» more  VLSID 1996»
15 years 2 months ago
Design of high performance two stage CMOS cascode op-amps with stable biasing
The technique of mirror biasing is introduced and applied to a very high gain two stage CMOS cascode op-amp, in order to desensitize its output voltage to bias variations. Various...
Pradip Mandal, V. Visvanathan