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172
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ICCAD
2003
IEEE
16 years 1 months ago
2003
IEEE
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...
153
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ASPDAC
2009
ACM
15 years 11 months ago
2009
ACM
Abstract— In an effort to make processors more power efficient scratch pad memory (SPM) have been proposed instead of caches, which can consume majority of processor power. Howe...
127
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ISCAS
2006
IEEE
15 years 11 months ago
2006
IEEE
Vertex texturing is state-of-the-art functionality of vertex. Thus, traditional texture caches used in RE are not the 3D geometry processor. However, it aggravates the always appli...
163
Voted
IPPS
2005
IEEE
2005
IEEE
A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms
15 years 10 months ago
In this paper, we describe a prototype software framework that implements a formalized methodology for partitioning computational intensive applications between reconfigurable har...
178
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SI3D
2005
ACM
15 years 10 months ago
2005
ACM
We present a simple yet effective snapping technique for constraining the motion of the cursor of an input device to the surface of 3D models whose geometry is arbitrarily deforme...