Sciweavers

187 search results - page 37 / 38
» Improving Memory Energy Using Access Pattern Classification
Sort
View
IJNSEC
2007
110views more  IJNSEC 2007»
14 years 9 months ago
A Light Weight Enhancement to RC4 Based Security for Resource Constrained Wireless Devices
The Wired Equivalent Privacy (WEP) uses the 64 bit RC4 secret key stream cipher as its layer 2 security protocol. Although the underlying RC4 cipher is secure, the potential reuse...
Chetan Nanjunda Mathur, K. P. Subbalakshmi
IPPS
2007
IEEE
15 years 3 months ago
Nonuniformly Communicating Noncontiguous Data: A Case Study with PETSc and MPI
Due to the complexity associated with developing parallel applications, scientists and engineers rely on highlevel software libraries such as PETSc, ScaLAPACK and PESSL to ease th...
Pavan Balaji, Darius Buntinas, Satish Balay, Barry...
RTSS
2006
IEEE
15 years 3 months ago
Tightening the Bounds on Feasible Preemption Points
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
ISCA
2008
IEEE
148views Hardware» more  ISCA 2008»
15 years 4 months ago
Atomic Vector Operations on Chip Multiprocessors
The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested th...
Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Y...
CCGRID
2011
IEEE
14 years 1 months ago
Small Discrete Fourier Transforms on GPUs
– Efficient implementations of the Discrete Fourier Transform (DFT) for GPUs provide good performance with large data sizes, but are not competitive with CPU code for small data ...
S. Mitra, A. Srinivasan