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» Instruction Level Distributed Processing
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IPPS
2007
IEEE
15 years 4 months ago
A Prototype Multithreaded Associative SIMD Processor
The performance of SIMD processors is often limited by the time it takes to transfer data between the centralized control unit and the parallel processor array. This is especially...
Kevin Schaffer, Robert A. Walker
75
Voted
SPDP
1991
IEEE
15 years 1 months ago
Local vs. global memory in the IBM RP3: experiments and performance modelling
A number of experiments regarding the placement of instructions, private data and shared data in the Non-Uniform-Memory-Access multiprocessor, RP3 has been performed. Three Scient...
Mats Brorsson
94
Voted
PDPTA
2010
14 years 8 months ago
A Novel Computation-to-core Mapping Scheme for Robust Facet Image Modeling on GPUs
Though the GPGPU concept is well-known in image processing, much more work remains to be done to fully exploit GPUs as an alternative computation engine. The difficulty is not refo...
Seung In Park, Yong Cao, Layne T. Watson
HPCA
2003
IEEE
15 years 10 months ago
Dynamic Optimization of Micro-Operations
Inherent within complex instruction set architectures such as x86 are inefficiencies that do not exist in a simpler ISAs. Modern x86 implementations decode instructions into one o...
Brian Slechta, David Crowe, Brian Fahs, Michael Fe...
ASPLOS
2004
ACM
15 years 3 months ago
An ultra low-power processor for sensor networks
We present a novel processor architecture designed specifically for use in low-power wireless sensor-network nodes. Our sensor network asynchronous processor (SNAP/LE) is based on...
Virantha N. Ekanayake, Clinton Kelly IV, Rajit Man...