2784 search results - page 133 / 557 » Instruction Level Parallelism |
135
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BIRTHDAY
2006
Springer
15 years 8 months ago
2006
Springer
We describe a gate level design of a FlexRay-like bus interface. An electronic control unit (ECU) is obtained by integrating this interface into the design of the verified VAMP pro...
142
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DSD
2008
IEEE
15 years 6 months ago
2008
IEEE
In this paper we present results of parallelization of Deblocking Filter (DF) of H.264 video codec on Decoupled Threaded Architecture (DTA). We parallelized the code trying to exp...
143
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IPPS
2007
IEEE
15 years 11 months ago
2007
IEEE
The performance of SIMD processors is often limited by the time it takes to transfer data between the centralized control unit and the parallel processor array. This is especially...
142
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PVM
2004
Springer
15 years 10 months ago
2004
Springer
On recent PC graphics cards, fully programmable parallel geometry and pixel units are available providing powerful instruction sets to perform arithmetic and logical operations. In...
131
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ICCD
2006
IEEE
16 years 1 months ago
2006
IEEE
—Current micro-architecture blindly uses the address in the program counter to fetch and execute instructions without validating its legitimacy. Whenever this blind-folded instru...