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» Instruction Level Parallelism
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CODES
2006
IEEE
15 years 10 months ago
Integrated analysis of communicating tasks in MPSoCs
Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication net...
Simon Schliecker, Matthias Ivers, Rolf Ernst
CLUSTER
2008
IEEE
15 years 5 months ago
Variable-grain and dynamic work generation for Minimal Unique Itemset mining
Abstract--SUDA2 is a recursive search algorithm for Minimal Unique Itemset detection. Such sets of items are formed via combinations of non-obvious attributes enabling individual r...
Paraskevas Yiapanis, David J. Haglin, Anna M. Mann...
IPPS
2007
IEEE
15 years 10 months ago
Model-Guided Empirical Optimization for Multimedia Extension Architectures: A Case Study
Compiler technology for multimedia extensions must effectively utilize not only the SIMD compute engines but also the various levels of the memory hierarchy: superword registers,...
Chun Chen, Jaewook Shin, Shiva Kintali, Jacqueline...
HCW
1999
IEEE
15 years 8 months ago
An On-Line Performance Visualization Technology
We present a new software technology for on-line performance analysis and visualization of complex parallel and distributed systems. Often heterogeneous, these systems need capabi...
Aleksandar M. Bakic, Matt W. Mutka, Diane T. Rover
EDOC
2007
IEEE
15 years 10 months ago
Implementing Business Conversations with Consistency Guarantees Using Message-Oriented Middleware
The paper considers distributed applications where interactions between constituent services take place via messages in an asynchronous environment with unpredictable communicatio...
Carlos Molina-Jiménez, Santosh K. Shrivasta...