60 search results - page 6 / 12 » Interface Design for Rationally Clocked GALS Systems |
101
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ISCAS
2005
IEEE
15 years 5 months ago
2005
IEEE
— Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because of disturbances that result from parasiti...
DAC
2000
ACM
16 years 18 days ago
2000
ACM
This paper presents a novel run-time dynamic voltage scaling scheme for low-power real-time systems. It employs software feedback control of supply voltage, which is applicable to...
132
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ICCD
1997
IEEE
15 years 3 months ago
1997
IEEE
Asynchronous systems are being viewed as an increasingly viable alternative to purely synchronous systems. This paper gives an overview of the current state of the art in practica...
119
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CHI
2006
ACM
16 years 1 days ago
2006
ACM
A problem with many of today's appliance interfaces is that they are inconsistent. For example, the procedure for setting the time on alarm clocks and VCRs differs, even amon...
ICCAD
2005
IEEE
15 years 5 months ago
2005
IEEE
— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...