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» JMOCHA: A Model Checking Tool that Exploits Design Structure
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VLSID
2003
IEEE
180views VLSI» more  VLSID 2003»
15 years 9 months ago
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
Pao-Ann Hsiung, Shu-Yu Cheng
JSA
2008
131views more  JSA 2008»
14 years 9 months ago
Formal verification of ASMs using MDGs
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...
Amjad Gawanmeh, Sofiène Tahar, Kirsten Wint...
USS
2004
14 years 10 months ago
TIED, LibsafePlus: Tools for Runtime Buffer Overflow Protection
Buffer overflow exploits make use of the treatment of strings in C as character arrays rather than as first-class objects. Manipulation of arrays as pointers and primitive pointer...
Kumar Avijit, Prateek Gupta, Deepak Gupta
ROOM
2000
14 years 10 months ago
Checking the Consistency of UML Class Diagrams Using Larch Prover
The Unified Modeling Language (UML) has been designed to be a full standard notation for Object-Oriented Modelling. UML is a rather complete set of notations, but it lacks of form...
Pascal André, Annya Romanczuk, Jean-Claude ...
ACMICEC
2007
ACM
102views ECommerce» more  ACMICEC 2007»
15 years 1 months ago
Security when people matter: structuring incentives for user behavior
Humans are "smart components" in a system, but cannot be directly programmed to perform; rather, their autonomy must be respected as a design constraint and incentives p...
Rick Wash, Jeffrey K. MacKie-Mason