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ANCS
2008
ACM
15 years 3 months ago
Low power architecture for high speed packet classification
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu
136
Voted
MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
15 years 8 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
ICPP
1993
IEEE
15 years 6 months ago
Scalability Study of the KSR-1
Scalability of parallel architectures is an interesting area of current research. Shared memory parallel programming is attractive stemming from its relative ease in transitioning...
Umakishore Ramachandran, Gautam Shah, Ravi Kumar, ...
169
Voted
TC
2011
14 years 8 months ago
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
131
Voted
ICDE
2007
IEEE
155views Database» more  ICDE 2007»
15 years 8 months ago
Query-Aware Sampling for Data Streams
Data Stream Management Systems are useful when large volumes of data need to be processed in real time. Examples include monitoring network traffic, monitoring financial transacti...
Theodore Johnson, S. Muthukrishnan, Vladislav Shka...