125 search results - page 9 / 25 » Loop Striping: Maximize Parallelism for Nested Loops |
IPPS
2002
IEEE
15 years 3 months ago
2002
IEEE
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs ...
83
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IPPS
2007
IEEE
15 years 4 months ago
2007
IEEE
With the increasing gap between processor speed and memory latency, the performance of data-dominated programs are becoming more reliant on fast data access, which can be improved...
185
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ICDE
2009
IEEE
15 years 12 months ago
2009
IEEE
Adaptive join algorithms have recently attracted a lot of attention in emerging applications where data is provided by autonomous data sources through heterogeneous network enviro...
113
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ICS
1999
Tsinghua U.
15 years 2 months ago
1999
Tsinghua U.
On modern computers, the performance of programs is often limited by memory latency rather than by processor cycle time. To reduce the impact of memory latency, the restructuring ...
ISCAPDCS
2001
14 years 11 months ago
2001
-Multi-dimensional applications, such as image processing and seismic analysis, usually require the optimized performance obtained from instruction-level parallelism. The critical ...