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95
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APCSAC
2006
IEEE
15 years 6 months ago
Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays
Abstract. Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affe...
Lih Wen Koh, Oliver Diessel
DSN
2006
IEEE
15 years 6 months ago
R-Opus: A Composite Framework for Application Performability and QoS in Shared Resource Pools
— We consider shared resource pool management taking into account per-application quality of service (QoS) requirements and server failures. Application QoS requirements are deï¬...
Ludmila Cherkasova, Jerome A. Rolia
98
Voted
ISCAS
2006
IEEE
111views Hardware» more  ISCAS 2006»
15 years 6 months ago
CMOS analog iterative decoders using margin propagation circuits
Abstract- Analog iterative decoders offer several advantages over their digital counterparts in terms of speed and power -A- log-MAP consumption. The current state of art CMOS anal...
S. Chakrabartty
ASAP
2005
IEEE
104views Hardware» more  ASAP 2005»
15 years 6 months ago
Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application
Users expect future handhelddevices to provide extended multimedia functionality and have long battery life. This type of application imposes heavy constraints on performance and ...
Andy Lambrechts, Praveen Raghavan, Anthony Leroy, ...
105
Voted
NCA
2005
IEEE
15 years 6 months ago
Reducing the Communication Cost via Chain Pattern Scheduling
This paper deals with general nested loops and proposes a novel scheduling methodology for reducing the communication cost of parallel programs. General loops contain complex loop...
Florina M. Ciorba, Theodore Andronikos, Ioannis Dr...