Many DSP and image processing embedded systems have hard memory constraints which makes it difficult to find a good task assignment and scheduling which fulfill these constrain...
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lava...
Data Stream Management Systems (DSMSs) must support optimized execution scheduling of multiple continuous queries on massive, and frequently bursty, data streams. Previous approac...
Schedulinglarge task graphsis an importantissue in parallel computingsince it allowsthe treatment of big size problems. In this paper we tackle the following problem: how to sched...
Michel Cosnard, Emmanuel Jeannot, Laurence Rougeot
In this paper, we follow a new path to arrive at the idea of a COMA — a Cache Only Memory Architecture. We show how the evolution of another architecture (ADARC) leads quite nat...