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DFT
2006
IEEE
203views VLSI» more  DFT 2006»
14 years 4 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
VTS
1997
IEEE
86views Hardware» more  VTS 1997»
14 years 3 months ago
Methods to reduce test application time for accumulator-based self-test
Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are no...
Albrecht P. Stroele, Frank Mayer
DATE
2008
IEEE
138views Hardware» more  DATE 2008»
14 years 5 months ago
Functional Self-Testing for Bus-Based Symmetric Multiprocessors
Functional, instruction-based self-testing of microprocessors has recently emerged as an effective alternative or supplement to other testing approaches, and is progressively adop...
Andreas Apostolakis, Dimitris Gizopoulos, Mihalis ...
VTS
2006
IEEE
102views Hardware» more  VTS 2006»
14 years 4 months ago
Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes
We consider self-testing of complete wireless nodes in the field through a low-energy software-based selftest (SBST) method. Energy consumption is optimized both for individual co...
Rong Zhang, Zeljko Zilic, Katarzyna Radecka
VTS
2005
IEEE
96views Hardware» more  VTS 2005»
14 years 4 months ago
Implementing a Scheme for External Deterministic Self-Test
A new method for test resource partitioning is introduced which keeps the design-for-test logic independent of the test set and moves the test pattern dependent information to an ...
Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valent...