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141
Voted
VTS
2006
IEEE
133views Hardware» more  VTS 2006»
15 years 6 months ago
PEAKASO: Peak-Temperature Aware Scan-Vector Optimization
— In this paper, an algorithm for scan vector ordering, PEAKASO, is proposed to minimize the peak temperature during scan testing. Given a circuit with scan and the scan vectors,...
Minsik Cho, David Z. Pan
122
Voted
ATS
2005
IEEE
91views Hardware» more  ATS 2005»
15 years 6 months ago
SOC Test Scheduling with Test Set Sharing and Broadcasting
11 Due to the increasing test data volume needed to test corebased System-on-Chip, several test scheduling techniques minimizing the test application time have been proposed. In co...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
79
Voted
DATE
2005
IEEE
105views Hardware» more  DATE 2005»
15 years 6 months ago
An Improved Multi-Level Framework for Force-Directed Placement
One of the greatest impediments to achieving high quality placements using force-directed methods lies in the large amount of overlap initially present in these techniques. This o...
Kristofer Vorwerk, Andrew A. Kennings
113
Voted
INFOCOM
2003
IEEE
15 years 6 months ago
Integrating effective-bandwidth-based QoS routing and best effort routing
—A methodology is presented for integrating effective-bandwidth-based routing for QoS-sensitive traffic and datagram routing of the best-effort traffic. To prevent excessive dela...
Stephen L. Spitler, Daniel C. Lee
118
Voted
DAC
1997
ACM
15 years 4 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...