1529 search results - page 47 / 306 » On Timing Analysis of Combinational Circuits |
DAC
1996
ACM
15 years 1 months ago
1996
ACM
This paper presents the design of a Videophone CoderDecoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (comple...
DAC
2008
ACM
14 years 11 months ago
2008
ACM
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
EH
1999
IEEE
15 years 2 months ago
1999
IEEE
An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16bit address space into an 8-bit one. The target technology is FPGA,...
IPPS
2007
IEEE
15 years 4 months ago
2007
IEEE
As real-time systems become more prevalent, there is a need to guarantee that these increasingly complex systems perform as designed. One technique involves a static analysis to p...
DAC
2003
ACM
15 years 10 months ago
2003
ACM
In the way they cope with variability, present-day methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important as...