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» On-line optimal timing control of switched systems
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DATE
2010
IEEE
154views Hardware» more  DATE 2010»
15 years 7 months ago
ERSA: Error Resilient System Architecture for probabilistic applications
There is a growing concern about the increasing vulnerability of future computing systems to errors in the underlying hardware. Traditional redundancy techniques are expensive for...
Larkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. J...
CCS
2008
ACM
15 years 3 months ago
Towards an efficient and language-agnostic compliance checker for trust negotiation systems
To ensure that a trust negotiation succeeds whenever possible, authorization policy compliance checkers must be able to find all minimal sets of their owners' credentials tha...
Adam J. Lee, Marianne Winslett
PPOPP
2005
ACM
15 years 7 months ago
Exposing disk layout to compiler for reducing energy consumption of parallel disk based systems
Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural level techniques to reduc...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir, A...
ET
2002
115views more  ET 2002»
15 years 1 months ago
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
JSAC
2010
153views more  JSAC 2010»
14 years 8 months ago
Autonomic traffic engineering for network robustness
Abstract--The continuously increasing complexity of communication networks and the increasing diversity and unpredictability of traffic demand has led to a consensus view that the ...
Ali Tizghadam, Alberto Leon-Garcia