36 search results - page 6 / 8 » One-Level Cache Memory Design for Scalable SMT Architectures |
IPPS
2010
IEEE
13 years 4 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
IEEEPACT
2008
IEEE
14 years 20 days ago
2008
IEEE
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
COMCOM
2002
13 years 6 months ago
2002
Abstract-We propose a new webserver architecture optimized for delivery of large, popular files. Delivery of such files currently pose a scalability problem for conventional conten...
CF
2010
ACM
13 years 11 months ago
2010
ACM
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
MICRO
2003
IEEE
13 years 11 months ago
2003
IEEE
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...