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» Ontology Mapping - An Integrated Approach
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ICICS
2009
Springer
15 years 4 months ago
Assessing Security Risk to a Network Using a Statistical Model of Attacker Community Competence
We propose a novel approach for statistical risk modeling of network attacks that lets an operator perform risk analysis using a data model and an impact model on top of an attack ...
Tomas Olsson
ICRA
2008
IEEE
163views Robotics» more  ICRA 2008»
15 years 4 months ago
Dealing with laser scanner failure: Mirrors and windows
— This paper addresses the problem of laser scanner failure on mirrors and windows. Mirrors and glasses are quite common objects that appear in our daily lives. However, while la...
Shao-Wen Yang, Chieh-Chih Wang
GLVLSI
2007
IEEE
328views VLSI» more  GLVLSI 2007»
15 years 4 months ago
New timing and routability driven placement algorithms for FPGA synthesis
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong H...
CODES
2006
IEEE
15 years 3 months ago
Layout aware design of mesh based NoC architectures
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
Krishnan Srinivasan, Karam S. Chatha
DFT
2006
IEEE
143views VLSI» more  DFT 2006»
15 years 3 months ago
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
Vijay K. Jain, Glenn H. Chapman