166 search results - page 4 / 34 » Optimal System-on-Chip Test Scheduling |
78
Voted
CCE
2004
15 years 3 months ago
2004
132
Voted
DFT
2006
IEEE
15 years 10 months ago
2006
IEEE
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
109
Voted
ECRTS
2003
IEEE
15 years 9 months ago
2003
IEEE
We present a sufficient linear-time schedulability test for preemptable, asynchronous, periodic task systems with arbitrary relative deadlines, scheduled on a uniprocessor by an ...
131
Voted
VLSID
2002
IEEE
16 years 4 months ago
2002
IEEE
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
157
click to vote
CODES
2011
IEEE
14 years 3 months ago
2011
IEEE
Reliability is a major requirement for most safety-related systems. To meet this requirement, fault-tolerant techniques such as hardware replication and software re-execution are ...