27 search results - page 6 / 6 » Optimization of Area and Performance by Processor-Like Recon... |
MICRO
2000
IEEE
14 years 11 months ago
2000
IEEE
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
102
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ET
2002
14 years 11 months ago
2002
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...