894 search results - page 22 / 179 » Optimizations for LTL Synthesis |
DATE
2007
IEEE
15 years 5 months ago
2007
IEEE
Conventional high-level synthesis algorithms usually employ multi-cycle operators to reduce the cycle length in order to improve the circuit performance. These operators need seve...
109
Voted
ECRTS
2002
IEEE
2002
IEEE
Managing Multi-Mode Tasks with Time Cost and Quality Levels using Optimal Discrete Control Synthesis
15 years 3 months ago
Real-time control systems are complex to design, and automation support is important. We are interested in systems with multiple tasks, each with multiple modes, implementing a fu...
89
Voted
DAC
1996
ACM
15 years 3 months ago
1996
ACM
Recent trends in the semiconductor industry have resulted in an increasing demand for low power circuits. POSE is a step in providing the EDA community and academia with an enviro...
ICCAD
2007
IEEE
2007
IEEE
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
15 years 7 months ago
—Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is...
ISCAS
2005
IEEE
15 years 4 months ago
2005
IEEE
Abstract— In this paper, we propose a sub-operation parallelism optimization algorithm in SIMD processor synthesis. Given an initial assembly code and timing constraints, our alg...