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» Optimizing Technology Mapping for FPGAs Using CAMs
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DAC
1996
ACM
15 years 1 months ago
Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design
In this paper, we study the problem of decomposing gates in fanin-unbounded or K-bounded networks such that the K-input LUT mapping solutions computed by a depthoptimal mapper hav...
Jason Cong, Yean-Yow Hwang
89
Voted
ERSA
2004
129views Hardware» more  ERSA 2004»
14 years 11 months ago
A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs
Platform FPGAs incorporate many different components, such as processor core(s), reconfigurable logic, memory, etc., onto a single chip. When an application is synthesized on platf...
Jingzhao Ou, Viktor K. Prasanna
FPGA
2010
ACM
182views FPGA» more  FPGA 2010»
14 years 7 months ago
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs
Metastability is a phenomenon that can cause system failures in digital circuits. It may occur whenever signals are being transmitted across asynchronous or unrelated clock domain...
Doris Chen, Deshanand Singh, Jeffrey Chromczak, Da...
91
Voted
ICVS
2001
Springer
15 years 1 months ago
Compiling SA-C Programs to FPGAs: Performance Results
Abstract. At the first ICVS, we presented SA-C (“sassy”), a singleassignment variant of the C programming language designed to exploit both coarse-grain and fine-grain parallel...
Bruce A. Draper, A. P. Wim Böhm, Jeffrey Hamm...
DATE
2000
IEEE
142views Hardware» more  DATE 2000»
15 years 1 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi