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» PRISM: An Integrated Architecture for Scalable Shared Memory
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DAC
2012
ACM
13 years 2 days ago
A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC
Diverse IP cores are integrated on a modern system-on-chip and share resources. Off-chip memory bandwidth is often the scarcest resource and requires careful allocation. Two of t...
Min Kyu Jeong, Mattan Erez, Chander Sudanthi, Nige...
MSS
1999
IEEE
166views Hardware» more  MSS 1999»
15 years 1 months ago
A 64-bit, Shared Disk File System for Linux
In computer systems today, speed and responsiveness is often determined by network and storage subsystem performance. Faster, more scalable networking interfaces like Fibre Channe...
Kenneth W. Preslan, Andrew P. Barry, Jonathan Bras...
CORR
2011
Springer
177views Education» more  CORR 2011»
14 years 4 months ago
Measuring NUMA effects with the STREAM benchmark
Modern high-end machines feature multiple processor packages, each of which contains multiple independent cores and integrated memory controllers connected directly to dedicated ph...
Lars Bergstrom
ANCS
2008
ACM
14 years 11 months ago
A programmable architecture for scalable and real-time network traffic measurements
Accurate and real-time traffic measurement is becoming increasingly critical for large variety of applications including accounting, bandwidth provisioning and security analysis. ...
Faisal Khan, Lihua Yuan, Chen-Nee Chuah, Soheil Gh...
RTAS
1997
IEEE
15 years 1 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford