Sciweavers

1075 search results - page 109 / 215
» Parallel Programming with Transactional Memory
Sort
View
ICDCS
1998
IEEE
15 years 9 months ago
Flexible Exception Handling in the OPERA Process Support System
Exceptions are one of the most pervasive problems in process support systems. In installations expected to handle a large number of processes, having exceptions is bound to be a n...
Claus Hagen, Gustavo Alonso
ICPADS
2005
IEEE
15 years 10 months ago
A Hybrid Web Server Architecture for e-Commerce Applications
The performance of an e-commerce application can be measured according to technical metrics but also following business indicators. The revenue obtained by a commercial web applic...
David Carrera, Vicenç Beltran, Jordi Torres...
CGO
2003
IEEE
15 years 10 months ago
Optimizing Memory Accesses For Spatial Computation
In this paper we present the internal representation and optimizations used by the CASH compiler for improving the memory parallelism of pointer-based programs. CASH uses an SSA-b...
Mihai Budiu, Seth Copen Goldstein
IPPS
2009
IEEE
15 years 11 months ago
Enabling high-performance memory migration for multithreaded applications on LINUX
As the number of cores per machine increases, memory architectures are being redesigned to avoid bus contention and sustain higher throughput needs. The emergence of Non-Uniform M...
Brice Goglin, Nathalie Furmento
HPDC
2007
IEEE
15 years 11 months ago
Feedback-directed thread scheduling with memory considerations
This paper describes a novel approach to generate an optimized schedule to run threads on distributed shared memory (DSM) systems. The approach relies upon a binary instrumentatio...
Fengguang Song, Shirley Moore, Jack Dongarra