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PACT
2005
Springer
15 years 3 months ago
Information Flow Analysis for VHDL
We describe a fragment of the hardware description language VHDL that is suitable for implementing the Advanced Encryption Standard algorithm. We then define an Information Flow a...
Terkel K. Tolstrup, Flemming Nielson, Hanne Riis N...
85
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FPGA
2009
ACM
273views FPGA» more  FPGA 2009»
15 years 4 months ago
A parallel/vectorized double-precision exponential core to accelerate computational science applications
Many natural processes exhibit exponential decay and, consequently, computational scientists make extensive use of e−x in computer simulation experiments. While it is common to ...
Robin Pottathuparambil, Ron Sass
ICCD
2002
IEEE
128views Hardware» more  ICCD 2002»
15 years 6 months ago
Subword Sorting with Versatile Permutation Instructions
Subword parallelism has succeeded in accelerating many multimedia applications. Subword permutation instructions have been proposed to efficiently rearrange subwords in or among r...
Zhijie Shi, Ruby B. Lee
PVM
1997
Springer
15 years 1 months ago
Embedding SCI into PVM
The extremely low latencies and high bandwidth results achievable with the Scalable Coherent Interface SCI at lowest level encourages its integration into existing Message Passin...
Markus Fischer, Jens Simon
FPGA
2004
ACM
174views FPGA» more  FPGA 2004»
15 years 3 months ago
A compiled accelerator for biological cell signaling simulations
The simulation of large systems of biochemical reactions is a key part of research into molecular signaling and information processing in biological cells. However, it can be impr...
John F. Keane, Christopher Bradley, Carl Ebeling