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ICASSP
2008
IEEE
15 years 9 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
CCGRID
2007
IEEE
15 years 9 months ago
Dynamic Malleability in Iterative MPI Applications
Malleability enables a parallel application’s execution system to split or merge processes modifying granularity. While process migration is widely used to adapt applications to...
Kaoutar El Maghraoui, Travis J. Desell, Boleslaw K...
EUROMICRO
2007
IEEE
15 years 9 months ago
Partial Verification of Software Components: Heuristics for Environment Construction
Code model checking of software components suffers from the well-known problem of state explosion when applied to highly parallel components, despite the fact that a single compon...
Pavel Parizek, Frantisek Plasil
HPDC
2007
IEEE
15 years 9 months ago
Precise and realistic utility functions for user-centric performance analysis of schedulers
Utility functions can be used to represent the value users attach to job completion as a function of turnaround time. Most previous scheduling research used simple synthetic repre...
Cynthia Bailey Lee, Allan Snavely
IPPS
2007
IEEE
15 years 9 months ago
Inverse Space-Filling Curve Partitioning of a Global Ocean Model
In this paper, we describe how inverse space-filling curve partitioning is used to increase the simulation rate of a global ocean model. Space-filling curve partitioning allows ...
John M. Dennis