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ISCA
2012
IEEE
260views Hardware» more  ISCA 2012»
13 years 11 days ago
A case for exploiting subarray-level parallelism (SALP) in DRAM
Modern DRAMs have multiple banks to serve multiple memory requests in parallel. However, when two requests go to the same bank, they have to be served serially, exacerbating the h...
Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Li...
PDP
2010
IEEE
15 years 4 months ago
Impact of Parallel Workloads on NoC Architecture Design
— Due to the multi-core processors, the importance of parallel workloads has increased considerably. However, manycore chips demand new interconnection strategies, since traditio...
Henrique Cota de Freitas, Lucas Mello Schnorr, Mar...
ICDCS
1998
IEEE
15 years 2 months ago
LBF: A Performance Metric for Program Reorganization
We introduce a new performance metric, called Load Balancing Factor (LBF), to assist programmers with evaluating different tuning alternatives. The LBF metric differs from traditi...
Hyeonsang Eom, Jeffrey K. Hollingsworth
ICPADS
2002
IEEE
15 years 2 months ago
Communication Pattern Based Methodology for Performance Analysis of Termination Detection Schemes
Efficient determination of processing termination at barrier synchronization points can occupy an important role in the overall throughput of parallel and distributed computing sy...
Yili Tseng, Ronald F. DeMara
ISPDC
2008
IEEE
15 years 4 months ago
Performance Analysis of Grid DAG Scheduling Algorithms using MONARC Simulation Tool
This paper presents a new approach for analyzing the performance of grid scheduling algorithms for tasks with dependencies. Finding the optimal procedures for DAG scheduling in Gr...
Florin Pop, Ciprian Dobre, Valentin Cristea