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ET
2002
84views more  ET 2002»
15 years 3 months ago
Hardware Generation of Random Single Input Change Test Sequences
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
René David, Patrick Girard, Christian Landr...
EUROPAR
1999
Springer
15 years 8 months ago
Consequences of Modern Hardware Design for Numerical Simulations and Their Realization in FEAST
This paper deals with the influence of hardware aspects of modern computer architectures to the design of software for numerical simulations. We present performance tests for vari...
Christian Becker, Susanne Kilian, Stefan Turek
SBCCI
2005
ACM
185views VLSI» more  SBCCI 2005»
15 years 9 months ago
Automatic generation of test sets for SBST of microprocessor IP cores
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
Ernesto Sánchez, Matteo Sonza Reorda, Giova...
138
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IEE
2010
185views more  IEE 2010»
15 years 2 months ago
Judy - a mutation testing tool for Java
Popular code coverage measures, such as branch coverage, are indicators of the thoroughness rather than the fault detection capability of test suites. Mutation testing is a fault-...
Lech Madeyski, N. Radyk
AIR
2005
99views more  AIR 2005»
15 years 4 months ago
Evolving General Term-Weighting Schemes for Information Retrieval: Tests on Larger Collections
Term-weighting schemes are vital to the performance of Information Retrieval models that use term frequency characteristics to determine the relevance of a document. The vector spa...
Ronan Cummins, Colm O'Riordan