Sciweavers

261 search results - page 10 / 53
» Polymorphic wavelet architectures using reconfigurable hardw...
Sort
View
56
Voted
ICCD
2000
IEEE
103views Hardware» more  ICCD 2000»
15 years 6 months ago
Efficient Place and Route for Pipeline Reconfigurable Architectures
In this paper, we present a fast and eficient compilation methodology for pipeline reconfigurable architectures. Our compiler back-end is much faster than conventional CAD tools, ...
Srihari Cadambi, Seth Copen Goldstein
FPL
2008
Springer
96views Hardware» more  FPL 2008»
14 years 11 months ago
Towards benchmarking energy efficiency of reconfigurable architectures
Energy research in reconfigurable architectures often involves legacy benchmarks such as the MCNC benchmarks. These benchmarks, however, are not well-suited for assessing energy c...
Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y....
ERSA
2009
107views Hardware» more  ERSA 2009»
14 years 7 months ago
Towards Effective Modeling and Programming Multi-core Tiled Reconfigurable Architectures
For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigur...
Kenneth C. Rovers, Marcel D. van de Burgwal, Jan K...
ERSA
2009
185views Hardware» more  ERSA 2009»
14 years 7 months ago
Woolcano: An Architecture And Tool Flow For Dynamic Instruction Set Extension On Xilinx Virtex-4 FX
In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Uni...
Mariusz Grad, Christian Plessl
IPPS
2007
IEEE
15 years 3 months ago
A General Purpose Partially Reconfigurable Processor Simulator (PReProS)
An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for ...
Alisson Vasconcelos De Brito, Matthias Kühnle...