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» Power Efficient Mediaprocessors: Design Space Exploration
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CODES
2006
IEEE
15 years 3 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
ICCD
2006
IEEE
118views Hardware» more  ICCD 2006»
15 years 6 months ago
A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models
—This paper presents a system-level Network-on-Chip modeling framework that integrates transaction-level model and analytical wire model for design space exploration. It enables ...
Jinwen Xi, Peixin Zhong
GECCO
2004
Springer
148views Optimization» more  GECCO 2004»
15 years 3 months ago
A Multi-objective Approach to Configuring Embedded System Architectures
Portable embedded systems are being driven by consumer demands to be thermally efficient, perform faster, and have longer battery life. To design such a system, various hardware un...
James Northern III, Michael A. Shanblatt
ICCV
2009
IEEE
14 years 7 months ago
Efficient human pose estimation via parsing a tree structure based human model
Human pose estimation is the task of determining the states (location, orientation and scale) of each body part. It is important for many vision understanding applications, e.g. v...
Xiaoqin Zhang, Changcheng Li, Xiaofeng Tong, Weimi...
ASAP
2007
IEEE
118views Hardware» more  ASAP 2007»
14 years 11 months ago
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...
Götz Kappen, S. el Bahri, O. Priebe, Tobias G...