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CASES
2010
ACM
14 years 7 months ago
Hardware trust implications of 3-D integration
3-D circuit-level integration is a chip fabrication technique in which two or more dies are stacked and combined into a single circuit through the use of vertical electroconductiv...
Ted Huffmire, Timothy E. Levin, Michael Bilzor, Cy...
69
Voted
CORR
2008
Springer
148views Education» more  CORR 2008»
14 years 9 months ago
Copper Electrodeposition for 3D Integration
Abstract-Two dimensional (2D) integration has been the traditional approach for IC integration. Increasing demands for providing electronic devices with superior performance and fu...
Rozalia Beica, Charles Sharbono, Tom Ritzdorf
DATE
2009
IEEE
155views Hardware» more  DATE 2009»
15 years 4 months ago
Dynamic thermal management in 3D multicore architectures
— Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architec...
Ayse Kivilcim Coskun, José L. Ayala, David ...
CLEIEJ
2010
14 years 7 months ago
3D-Via Driven Partitioning for 3D VLSI Integrated Circuits
A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. Howeve...
Sandro Sawicki, Gustavo Wilke, Marcelo O. Johann, ...
SLIP
2009
ACM
15 years 4 months ago
Integrated interlayer via planning and pin assignment for 3D ICs
As technology advances, 3D ICs are introduced for alleviating the interconnect problem coming with shrinking feature size and increasing integration density. In 3D ICs, one of the...
Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto