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» Quasi-Resonant Interconnects: A Low Power Design Methodology
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115
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VLSISP
2008
147views more  VLSISP 2008»
14 years 11 months ago
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...
Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sun...
124
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VLSID
2010
IEEE
173views VLSI» more  VLSID 2010»
15 years 4 months ago
Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
Mohammad Arjomand, Hamid Sarbazi-Azad
94
Voted
ISCAS
2003
IEEE
77views Hardware» more  ISCAS 2003»
15 years 5 months ago
Inductive interconnect width optimization for low power
The width of an interconnect line a ects the total power consumed by a circuit. A tradeo exists, however, between the dynamic power and the short-circuit power in determining the ...
Magdy A. El-Moursy, Eby G. Friedman
105
Voted
ISLPED
2010
ACM
236views Hardware» more  ISLPED 2010»
15 years 19 days ago
Analysis and design of ultra low power thermoelectric energy harvesting systems
Thermal energy harvesting using micro-scale thermoelectric generators is a promising approach to alleviate the power supply challenge in ultra low power systems. In thermal energy...
Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaush...
ANCS
2009
ACM
14 years 10 months ago
Design of a scalable nanophotonic interconnect for future multicores
As communication-centric computing paradigm gathers momentum due to increased wire delays and excess power dissipation with technology scaling, researchers have focused their atte...
Avinash Karanth Kodi, Randy Morris