59 search results - page 11 / 12 » Runtime leakage power estimation technique for combinational... |
DAC
1996
ACM
13 years 10 months ago
1996
ACM
A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced nois...
DAC
2000
ACM
14 years 7 months ago
2000
ACM
Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In ...
DAC
2010
ACM
13 years 6 months ago
2010
ACM
Many DTM schemes rely heavily on the accurate knowledge of the chip's dynamic thermal state to make optimal performance/ temperature trade-off decisions. This information is ...
VTS
2006
IEEE
14 years 8 days ago
2006
IEEE
A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, ce...
DAC
2006
ACM
14 years 7 months ago
2006
ACM
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...