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» Scaling, Power and the Future of CMOS
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ISPASS
2005
IEEE
15 years 3 months ago
Partitioning Multi-Threaded Processors with a Large Number of Threads
Today’s general-purpose processors are increasingly using multithreading in order to better leverage the additional on-chip real estate available with each technology generation...
Ali El-Moursy, Rajeev Garg, David H. Albonesi, San...
MICRO
2009
IEEE
99views Hardware» more  MICRO 2009»
15 years 4 months ago
Low-cost router microarchitecture for on-chip networks
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
John Kim
IPPS
2007
IEEE
15 years 3 months ago
File Creation Strategies in a Distributed Metadata File System
As computing breaches petascale limits both in processor performance and storage capacity, the only way that current and future gains in performance can be achieved is by increasi...
Ananth Devulapalli, Pete Wyckoff
88
Voted
SLIP
2009
ACM
15 years 4 months ago
Prediction of high-performance on-chip global interconnection
Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires. In this paper, we give an overview of curre...
Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin...
IPPS
2008
IEEE
15 years 4 months ago
Massive supercomputing coping with heterogeneity of modern accelerators
Heterogeneous supercomputers with combined general purpose and accelerated CPUs promise to be the future major architecture due to their wideranging generality and superior perfor...
Toshio Endo, Satoshi Matsuoka