605 search results - page 55 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
ICPP
1995
IEEE
15 years 1 months ago
1995
IEEE
— Skewed-associative caches use several hash functions to reduce collisions in caches without increasing the associativity. This technique can increase the hit ratio of a cache w...
IPPS
2007
IEEE
15 years 4 months ago
2007
IEEE
The performance of SIMD processors is often limited by the time it takes to transfer data between the centralized control unit and the parallel processor array. This is especially...
SCOPES
2004
Springer
15 years 3 months ago
2004
Springer
Digital signal processing applications are implemented in embedded systems with fixed-point arithmetic to minimize the cost and the power consumption. To reduce the application ti...
CF
2005
ACM
14 years 11 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
ACSC
2004
IEEE
15 years 1 months ago
2004
IEEE
This paper reports on an experiment to determine the optimal parameters for a speech recogniser that is part of a computer aided instruction system for assisting learners of Engli...