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APCSAC
2001
IEEE
15 years 5 months ago
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
Kenji Watanabe, Wanming Chu, Yamin Li
CASES
2001
ACM
15 years 5 months ago
A system-on-a-chip lock cache with task preemption support
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory System-on-a-Chip implementation. These overheads are observed in terms of loc...
Bilge Saglam Akgul, Jaehwan Lee, Vincent John Moon...
ICDCS
2010
IEEE
15 years 5 months ago
B-SUB: A Practical Bloom-Filter-Based Publish-Subscribe System for Human Networks
—The adoption of portable wireless devices is rapidly rising. The demand for efficient communication protocols amongst these devices is pressing. In this paper, we present a con...
Yaxiong Zhao, Jie Wu
FPGA
2000
ACM
161views FPGA» more  FPGA 2000»
15 years 5 months ago
The effect of LUT and cluster size on deep-submicron FPGA performance and density
In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cl...
Elias Ahmed, Jonathan Rose
FPGA
2000
ACM
122views FPGA» more  FPGA 2000»
15 years 5 months ago
A reconfigurable multi-function computing cache architecture
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
Huesung Kim, Arun K. Somani, Akhilesh Tyagi
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