1304 search results - page 107 / 261 » Simulation of Soliton Circuits |
DAC
2008
ACM
15 years 11 months ago
2008
ACM
The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires at...
DAC
2004
ACM
15 years 11 months ago
2004
ACM
With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, ...
ISCAS
2006
IEEE
15 years 4 months ago
2006
IEEE
Abstract- Analog iterative decoders offer several advantages over their digital counterparts in terms of speed and power -A- log-MAP consumption. The current state of art CMOS anal...
ASPDAC
2006
ACM
15 years 4 months ago
2006
ACM
— Sakurai-Newton (SN) delay metric [1] is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that t...
EMMCVPR
2011
Springer
13 years 10 months ago
2011
Springer
The challenge of recovering the topology of massive neuronal circuits can potentially be met by high throughput Electron Microscopy (EM) imagery. Segmenting a 3-dimensional stack o...