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    ICCAD
    1993
    IEEE
    101views Hardware» more  ICCAD 1993»
    Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits
    15 years 10 months ago
    Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits
    Download  www.eecg.utoronto.ca
    Kerry S. Lowe, P. Glenn Gulak
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    INFOCOM
    1990
    IEEE
    77views Communications» more  INFOCOM 1990»
    Performance Analysis of Banyan Networks Based on Buffers of Various Sizes
    15 years 10 months ago
    Performance Analysis of Banyan Networks Based on Buffers of Various Sizes
    Download  www.lehigh.edu
    Arindam Saha, Meghanad D. Wagh
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    ICCAD
    1997
    IEEE
    87views Hardware» more  ICCAD 1997»
    A new approach to simultaneous buffer insertion and wire sizing
    15 years 9 months ago
    A new approach to simultaneous buffer insertion and wire sizing
    Download  www.cs.ucr.edu
    Chris C. N. Chu, D. F. Wong
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    ICCAD
    1995
    IEEE
    79views Hardware» more  ICCAD 1995»
    Optimal wire sizing and buffer insertion for low power and a generalized delay model
    15 years 9 months ago
    Optimal wire sizing and buffer insertion for low power and a generalized delay model
    Download  www.cs.uic.edu
    John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
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    IEICET
    2006
    53views more  IEICET 2006»
    Round-Robin Selection with Adaptable Frame-Size for Combined Input-Crosspoint Buffered Packet Switches
    15 years 5 months ago
    Round-Robin Selection with Adaptable Frame-Size for Combined Input-Crosspoint Buffered Packet Switches
    Download  web.njit.edu
    Roberto Rojas-Cessa, Zhen Guo
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