87 search results - page 13 / 18 » Synthesis of Testable RTL Designs |
ASPDAC
2012
ACM
13 years 5 months ago
2012
ACM
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
FPL
2005
Springer
15 years 2 months ago
2005
Springer
The paper analyses and compares alternative iterative and recursive implementations of FPGA circuits for various problems. Two types of recursive calls have been examined, namely ...
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
DAC
1996
ACM
15 years 1 months ago
1996
ACM
This paper presents the design of a Videophone CoderDecoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (comple...
ASPDAC
2009
ACM
15 years 3 months ago
2009
ACM
— As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. In the presence of process variations, wo...