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EMSOFT
2006
Springer
15 years 9 months ago
Modeling a system controller for timing analysis
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...
Stephan Thesing
FASE
2006
Springer
15 years 9 months ago
Regular Inference for State Machines with Parameters
Techniques for inferring a regular language, in the form of a finite automaton, from a sufficiently large sample of accepted and nonaccepted input words, have been employed to cons...
Therese Berg, Bengt Jonsson, Harald Raffelt
ASPDAC
2001
ACM
130views Hardware» more  ASPDAC 2001»
15 years 8 months ago
Area/delay estimation for digital signal processor cores
Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and...
Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa...
FPGA
2000
ACM
161views FPGA» more  FPGA 2000»
15 years 8 months ago
The effect of LUT and cluster size on deep-submicron FPGA performance and density
In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cl...
Elias Ahmed, Jonathan Rose
SIGMETRICS
1998
ACM
15 years 8 months ago
Self-Similarity in File Systems
We demonstrate that high-level le system events exhibit selfsimilar behaviour, but only for short-term time scales of approximately under a day. We do so through the analysis of f...
Steven D. Gribble, Gurmeet Singh Manku, Drew S. Ro...